A programmable logic device (PLD) is a digital integrated circuit capable of being programmed to provide a variety of different logic functions. A PLD generally includes AND gates, OR gates, and Input/Output buffers, and functions differently depending on how it is programmed. The programming is achieved using on-chip fuses, EPROM (UV erasable programmable read-only memory) circuits, EEPROM (electrically erasable programmable read-only memory) circuits, and RAM (random access memory) circuits which programmably create data paths and logic functions within the device that are specific to the user's design.
State of the Art PLDs make use of one or more non-volatile memory cell (e.g. EPROM, EEPROM, Flash EPROM, or Flash EEPROM) arrays so that they can retain their configuration memory during power-down. Typically, these arrays are erasable, thereby allowing the desired functionality of the PLD to be re-programmed many times. This programmability makes a PLD family a flexible and powerful tool for a large number of unique applications where a common PLD is employed and only the chip's internal programming is varied.
Typically, verification is required after programming to ensure that the memory cells have been properly programmed and that the PLD functions according to the design specification. Verification of a PLD involves a combination of in-circuit functional testing, simulation, timing analysis, and memory cell verification. Memory cell verification is especially important in that it determines whether the PLD has been programmed correctly according to the design specification, and thus must be performed before shipping to a user or using the device for an actual application.
In integrated circuit testing, a technique called “boundary scan” has been developed to define a standard test logic architecture for implementing boundary scan functions which can be included in an integrated circuit for the purpose of testing the integrated circuit. This standard architecture was approved on Feb. 15, 1990 by the Institute of Electrical and Electronics Engineers (IEEE) and is commonly referred to as JTAG (Joint Test Action Group) or IEEE Standard 1149.1.
Originally, the JTAG standard created a means of verifying the integrity of traces between components on an assembled printed circuit board. This was accomplished by providing a standard architecture and a set of mandatory public instructions that all vendors claiming conformance to IEEE standard 1149.1 had to support.
Test programs can be written in accordance with the JTAG standard to program, pattern verify and functionally verify a programmable logic device. These programs can become large and can require large amounts of computer resources to store and execute. Prior art methods that attempted to optimize program code included using control-flow analysis on conditional statements such as IF-THEN and GOTO statements found in the source code or intermediate code to look for loops. Then the process attempted to create a FOR or WHILE loop by analyzing the beginning and end data conditions in the code to determine the loop index.
The prior art optimization methods provide no benefit to program source code that does not have conditional statements. Thus, if the code did not have IF-THEN statements, a loop could not be deduced and no optimization was performed.